A2601

A2601 is an FPGA-based clone of the legendary ATARI 2600 video console, developed completely by myself, including VHDL code and a custom PCB.

A2601 Rev B Homebrew PCB Installed in Plastic Case

A2601 Complete View Running Donkey Kong

A2601 Case Closeup

A2601 Running Pitfall

A2601 Running Keystone Kapers

A2601 Running Track and Field

A2601 Running Space Shuttle

A2601 Running River Raid

A2601 Running Pressure Cooker

Features

• Faithful FPGA implementation of the 6502 CPU and TIA (Television Interface Adapter) custom chip.
• Composite Video (currently NTSC only) and Audio output.
• DB9 connector for a MegaDrive/Genesis joypad.
• On-board 512Kb Flash memory for storing cartridge roms.
• Support for most bankswitching schemes used by original game cartridges.
• Design fits in a 100K-gate Spartan-3E FPGA.
• Custom PCB dimensions: 3.25″ by 2.5″.
• Complete VHDL source code available under GPL.

Videos

All game videos and screenshots featured on this page have been shot using a digital camera pointed towards an LCD TV connected to A2601.

 

How to use

A2601 Rev B PCB contains the following connectors:

• Composite Video (Standard Phono Connector)
• Audio (Standard Phono Connector)
• Power (9V, positive inside)
• Joypad (DB9, MegaDrive/Genesis)

The B button on the joypad acts as the fire button. The Start button works as the “Game Reset” button. When the A button down is held down, the direction buttons function as the switches on the console main unit (i.e. “Difficulty”, “Select”, etc.). Holding the C button down and pressing left or right moves to the previous or the next game on the flash memory, respectively.

Technical Information

A2601 Rev B Schematics Sheet 1

A2601 Rev B Schematics Sheet 2

A2601 Rev B Schematics Sheet 3

A2601 Rev B Board contains a TQFP 144-pin Spartan-3E FPGA, an XCF01 Configuration PROM, a 29W040B Flash Memory. The on-board JTAG connector allows programming of both the FPGA and the Configuration PROM. There are 4 linear voltage regulators on the board, supplying 5V, 3.3V, 2.5V and 1.2V. A 14.318 Mhz oscillator supplies the main clock signal for the FPGA.

The video circuitry consists of an 8-bit R-2R resistor ladder DAC with a FMS6141 active SDTV video filter output stage. Similarly, the audio circuity is a 5-bit R-2R resistor ladder DAC plus a transistor buffer output stage.

The joypad port is powered through the 5V voltage regulator on board. Resistor voltage-divider circuitry is used to translate joypad output levels to FPGA-safe levels. A transistor buffer is used to drive the SEL line on the joypad side.

To program the 29W040B flash on-board, a specialized FPGA design is used to read commands and data from the Xilinx JTAG port (see the Flash directory in the source code archive). A Python script called bin2xsvf.py is provided to convert binary files to .xsvf files suitable for use with Xilinx Impact software to program the flash memory in conjuction with the specialized design.

The board draws about 85ma of current from the 9V power input (power LED excluded).  

VHDL source code provided includes implementation of the 6502(7) CPU, the TIA, the 6532 RIOT, additional audio/video/joypad circuitry and bankswitching schemes plus additional RAM used by some game cartridges. Test benches are supplied for all main components (although they may be slightly out of date).

The 6502 core has been developed from scratch for this project by myself. It contains hand-crafted finite state machine and controls that implement all documented 6502 opcodes. It synthesizes quickly and has good performance in the simulator. The 6502 core is available under GPL just like the rest of the A2601 source code.

The TIA implementation digitally synthesizes NTSC composite video signal via a lookup table that contains a sequence of values that signifies a sine wave at correct phase for each one of the 16 chrominance values selectable in the TIA. A Xilinx DCM multiplies the input clock by four to improve the temporal resolution of the signal. An alternative would be to use a sine lookup table stored in FPGA built-in memory to synthesize the signal. With an improved DAC, this method could enable synthesis of PAL and NTSC signals from a common clock source.

You should be able to synthesize the A2601 in Xilinx ISE without any major problems. Two top level entities are provided: One reads cartridge ROM data from on-board flash memory, the other stores the data in the FPGA built-in SRAM. It is also possible to run A2601 sources in a VHDL simulator. Some helper utilities and a test bench are provided for this purpose in the util directory.

Download

A2601 Release 0.1.0 (Includes VHDL sources and Python script utilities)

Limitations (Future Work)

• PAL video output not supported.
• Starpath cassette loader not supported.
• Undocumented 6502 instructions are not implemented.
• Cosmic Ark starfield effect does not work at the moment.

Background

Most of the work on the FPGA side of A2601 was completed in about three months by 2006, at which point the A2601 was running fine in the simulator. In the following weeks, I first designed and built a generic Spartan-3E FPGA board and a couple of addons for it that contained video and audio output circuitry. Once I got the A2601 to work on this board, I went on to design and build the Rev A board with on-board flash memory. This board was somewhat larger than the current Rev B board as it was designed to fit into a larger plastic case, despite containing a smaller VQFP 100-pin Spartan-3E. It worked quite well, but unfortunately it did not survive, since my PCB making techniques were not as good back then. Recently, I decided to revisit this project and decided to redo the board layout and switch to a MegaDrive/Genesis joypad port, and the Rev B board documented on this page is the result.

Disclaimer

This information here is provided AS IS without any express or implied warranties. While every effort has been taken to ensure the accuracy of the information contained in this text, the author assumes no responsibility for errors or omissions, or for damages resulting from the use of the information contained herein. I will not be held responsible for any damages or costs which might occur as a result of anything related to projects described or referred to on this page. You are not allowed to use information contained in these pages for commercial purposes without my written authorization.