Posted by retromaster on August 22, 2011
Here is today’s second post: Another update on Cumulus.
First, the bad news: It looks like with the most recent change to CumuluBus, Cumulus bus errors were greatly reduced, but not completely eliminated. This is the case with the long cable setup.
Now the good news: I have tried the short cable setup (using the two closely-located connectors on the IDE cable), and during extensive testing, I have not encountered any bus-related issues.
What does this mean? It means that on some Orics the long cable setup may not work properly. In these cases, Cumulus will most probably still work fine in the short cable setup, though. It will be a somewhat inconvenient, though, as the cable length is not more than 10cms.
Why does this happen? Here is my guess:
The CPLD used in the Cumulus (XC95XL series) is a relatively modern part (at least compared to the Oric, that is). It has pin signal rise times in the range of a few nanoseconds.
In the current Cumulus design, the CPLD is connected to the data bus over a level-shifter IC (also w/ fast rise times) and directly connected to most of the bus control signals. The connection is by means of the 80-wire IDE cable. When the length of this cable exceeds a certain threshold, the cable starts to exhibit “transmission line” effects. Without the necessary termination on both ends of the cable, these effects cause significant signal integrity issues.
Even with the “SLOW” rise time setting on the output drivers, the XC95XL is fast enough to limit the length of the cable to just about 10cms.
I have to admit that I have overlooked this aspect of the design. I thought that since the frequencies on the Oric bus are so low, there would not be problems over a long cable. However, I failed to see that it is the rise time that’s the real governing parameter here, which was a mistake. This is most likely why things go wrong with the long cable setup.
One way of solving this problem could be by adding “slow” (74hc or 4000-series CMOS) buffers on the Cumulus side. Since these parts have much higher rise times, the permitted cable could be much longer. An additional advantage is that this way, possibly, CumuluBus could be eliminated! However, it would take a significant redesign effort, and it would enlarge the main PCB by quite a bit. To tell the truth, I am not really motivated to go through another design cycle, especially considering that Cumulus seems to work fine with the short cable setup.
Posted in Projects, Retrocomputing | Tagged: CPLD, CumuluBus, Cumulus, Floppy Emulator, rise time, signal integrity, transmission line, XC95, XC95144XL | 5 Comments »
Posted by retromaster on October 13, 2010
Cumulus Prototype Board Assembly Progress
Here is a picture of the Cumulus prototype board in its most current state. It is almost fully populated, except for the socket for the 28C EEPROM (I’ve run out of suitable sockets, it seems) and the HCT221 circuitry for MAP signal timing. The CPLD is available through JTAG and the PIC is accessible through ICSP. It took a while to get to this stage, as quite a few things got in the way and others simply went wrong… but now, everything seems to be back on track.
So, what were the problems? First of all, my JTAG Cable decided it won’t work any more… It may have something to do with all the abuse it had to withstand . Upon building a new one, I got the CPLD connection to work. Very good.
Then I went on to trying the ICSP connection to the 18F46K20, which did not work (to my surprise). So, I spent about a week, debugging on and off, where I checked all the connections, available schematics, etc. The Microchip starter kit schematics had a 8.2V zener diode on the MCLR pin, (my first thought was that was what was missing), but it ultimately turned out to be unnecessary with the PicKit 2, as long as PIC 18F K Series configuration was selected in the software. Finally, I built a couple of very simple boards, basically only with the PIC and ICSP connector on them, just to test the connection to PicKit 2. Those boards worked absolutely fine… Another round of checking, and it turned out that the problem was a fault on the Cumulus prototype board, where the PGD pin had a tiny short to ground. I have no idea how it slipped the first time, but it did. Anyway, now, ICSP is working fine.
So, now I can proceed in two directions. I can finish populating the board, write an Oric test program to the EEPROM (something simple that prints out a text message) and test that the Oric Bus interface is working fine. I can also go on with the UI board, and get the LCD and buttons on it to work, which should be very helpful with the debugging. Hopefully, whichever path I take, things will go a bit more smoothly this time.
Posted in Homebrew PCBs, Projects, Retrocomputing | Tagged: 18F46K20, CPLD, Cumulus, Floppy Emulator, ICSP, JTAG, Microchip, PCB, PIC, PIC18, XC95144XL, Xilinx | Leave a Comment »